Conference proceeding
A wave-pipelined router architecture using ternary associative memory
Proceedings of the 10th Great Lakes symposium on vlsi, pp.67-70
GLSVLSI '00
03/02/2000
Handle:
https://hdl.handle.net/2376/115756
Abstract
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time and power. The design approach considered in this paper allows the propagation of data from stage to stage to occur without the use of intermediate latches. Control signals are used to ensure that intermixing of data waves does not occur. The results of the study show that wave-pipelining helps to reduce the clock period.
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Details
- Title
- A wave-pipelined router architecture using ternary associative memory
- Creators
- José Delgado-FriasJabulani NyathiLaxmi Bhuyan
- Publication Details
- Proceedings of the 10th Great Lakes symposium on vlsi, pp.67-70
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Series
- GLSVLSI '00
- Publisher
- ACM
- Identifiers
- 99900548104301842
- Language
- English
- Resource Type
- Conference proceeding