Conference proceeding
Novel interconnect infrastructures for massive multicore chips - an overview
2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2777-2780
05/2008
Handle:
https://hdl.handle.net/2376/114766
Abstract
With the well-known trend of CMOS scaling as per Moore's law, traditional on-chip interconnect systems are reaching the point of having a very limited ability to meet the performance needs and specifications of systems-on-chip (SoCs). The conventional two-dimensional (2D) copper-based IC has inherent limitations due to the geometrical constraints of the planar structure. Innovative interconnect paradigms based on optical technologies, RF/wireless, carbon nanotubes, or 3D integration are promising alternatives that may indeed overcome the challenges encountered. In this paper we present an overview of different emerging non-traditional approaches to achieve massive degree of integration in a single chip. The advantages and underlying challenges of each method are highlighted.
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Details
- Title
- Novel interconnect infrastructures for massive multicore chips - an overview
- Creators
- P.P Pande - Sch. Of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WAA Ganguly - Sch. Of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WAB Belzer - Sch. Of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WAA NojehA Ivanov
- Publication Details
- 2008 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2777-2780
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Publisher
- IEEE
- Identifiers
- 99900547502601842
- Language
- English
- Resource Type
- Conference proceeding