Dissertation
A 5 GHZ low power, low jitter and fast settling phase locked loop architecutre [that is, architecture] for wireline and wireless transceiver
Washington State University
Doctor of Philosophy (PhD), Washington State University
08/2008
DOI:
https://doi.org/10.7273/000005843
Abstract
While significant research has already been poured into signal generation via the phase locked loop (PLL) and circuit methods to improve the PLL phase noise, constant desire for further improvement and higher data bandwidth demands more rigorous and novel improvements. In both wireline and wireless communication, the data bandwidth is heavily dependent on the quality of the PLL; however, PLLs come with their own unique set of challenges. They inherently take a long time to lock and require a very low phase noise voltage controlled oscillator (VCO) performance in a potentially noisy environment. They consume significant DC power, demand large silicon die area and force many trade-offs between key performance parameters. This intricacy puts wireless and wireline applications in an unenviable position, as they are strictly driven by highly integrated low power, low cost and high performance operations. Low-power constraints demand PLLs to be turned off during inactivity, but then require it to acquire lock swiftly when turned back on. Therefore, investigation of low cost, low power and high quality novel fast locking PLLs are driven by the insatiable demand of state-of-the-art wideband applications. This dissertation presents a low power PLL architecture with adaptive bandwidth control to enable fast settling and lock time, a novel load independent switched LC VCO, a low spur and glitch compensated dynamic replica-based current steering charge pump and an optimized very low power frequency divider to achieve sub-ps jitter performance in a 0.18-[mu]m process CMOS technology. Consuming 11mW of total power from 1.5V supply, the PLL achieves sub-[mu]s settling time, worst case reference spurs below 64 dB with worst case integrated RMS jitter of less than 2 ps and deterministic jitter of less than 7 ps in a noisy packaged environment. The PLL phase noise is lower than 120 dBc/Hz, at 1 MHz frequency offset from the carrier, over the tuning range. The PLL is designed with nominal loop bandwidth of 1 MHz. This dissertation consists of theoretical details of several novel VCO designs, novel glitch compensated charge-pump architecture and novel adaptive bandwidth mechanism for the PLL. The dissertation includes culmination of works from published or to be published peer review journal and conferences.
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Details
- Title
- A 5 GHZ low power, low jitter and fast settling phase locked loop architecutre [that is, architecture] for wireline and wireless transceiver
- Creators
- Parag Upadhyaya
- Contributors
- Deukhyoun Heo (Chair)
- Awarding Institution
- Washington State University
- Academic Unit
- School of Electrical Engineering and Computer Science
- Theses and Dissertations
- Doctor of Philosophy (PhD), Washington State University
- Publisher
- Washington State University
- Number of pages
- 107
- Identifiers
- 99901055140301842
- Language
- English
- Resource Type
- Dissertation