AI-ASSISTED BLACK-BOX OPTIMIZATION TECHNIQUES FOR HIGH-SPEED CIRCUITS AND SYSTEMS

Shrestha Bansal

doi:10.7273/000006912

Rapidly increasing demand for computing has led to the shrinkage of semiconductor technology nodes keeping up with Moore’s law. However, as we approach sub-nm regimes, this reduction of device sizes coupled with high-frequency applications have led to various challenges that need to be mitigated on device or circuit or system level to alleviate the overall system performance. CMOS circuits and systems are not only affected by dynamic effects such as input signal distortion, channel noise and process, voltage and temperature variations, but also by static effects such as device mismatch, channel-length modulation, random offsets, and gain errors. While static non-linearities can be overcome by digital calibration or look-up-table (LUT) based calibration, dynamic non-linearities need some kind of background calibration where a number of parameters need to be tuned at run-time to optimize their performance. Circuit based optimization techniques are highly system dependent and therefore are limited in their scope. In the recent years, there has been an increased focus on model-free artificial intelligence (AI) assisted optimization methods that be generalized to learn from and optimize a wider range of high-speed systems, making automated room-temperature control a formidable solution for the decades to come. In this dissertation, AI-assisted closed-loop optimization techniques are presented which treat the system-under-test as a black-box, eliminating the need for computationally complex system modelling and increasing the scope of these optimizers to a range of circuits and systems ranging from high-speed transceivers to cryogenic temperature electronics. The devised optimization techniques are extensively tested on high-speed CMOS and superconducting analog-to-digital converters (ADCs), Gallium Nitride (GaN) multi-input wideband power amplifiers (PA), and receiver systems for high-speed wireless communications. The presented closed-loop, automated, multi-parameter optimization approaches are computationally efficient, low-area, low-power and reduces the optimization time many folds, while improving the overall system performance. To further demonstrate the effectiveness of this optimization system, a CMOS-based application specific integrated circuit (ASIC) implementation is also realized which can be used as a plug-and-play device in closed loop with the actual system to optimize system parameters such as gain, offset, phase, etc to enhance the system performance as well as to tackle extrinsic effects on the system such as slow temperature variation, all while saving significant costs to the manufacturers. A hybrid particle swarm optimization and gradient descent algorithm is designed and shown to optimize multiple parameters of CMOS ADCs. This algorithm has further been modified and shown to optimize a series of current biases of a superconducting flash ADC, reducing its calibration time 12X versus the prior state of the art. Extremum seeking algorithm has also been demonstrated to suppress second order harmonics in a wideband multi-input PA by controlling the amplitude and phase of an externally injected signal. Finally, we implement these algorithms as ASIC and fabricate the chip to perform closed-loop optimization. The designed chip utilizes PSO-GD to perform foreground calibration and ES to perform background calibration. ES controller is also shown to perform automatic beam tracking for a conformal antenna array receiver. The total power consumption of the chip is 87.70 mW and occupies an active area of 0.23 mm2. We demonstrate the effectiveness of this chip by optimizing multiple cost function which accurately model the types of non-linearities encountered in high-speed circuits and systems.

AI-ASSISTED BLACK-BOX OPTIMIZATION TECHNIQUES FOR HIGH-SPEED CIRCUITS AND SYSTEMS

Files and links (1)

Abstract

Metrics

Details