Dissertation
Design Space Explorationfor Wireless Network-on-Chip Architectures
Doctor of Philosophy (PhD), Washington State University
01/2014
Handle:
https://hdl.handle.net/2376/111869
Abstract
The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern massive multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multi-hop metal/dielectric based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon Nanotube (CNT) or millimeter (mm)-wave metal antennas are shown to outperform traditional wire based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies can be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This thesis advocates adoption of such complex network based architectures to design wireless NoCs. This thesis presents a detailed performance analysis of small-world network enabled wireless NoC architectures in terms of achievable bandwidth, energy dissipation, thermal profiles and fault tolerance. The wireless NoC outperforms traditional wireline mesh architecture in terms of all the above-mentioned performance metrics. It also minimizes the effect of wireless link failures on the performance of the NoC. Through cycle accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of a high degree of link failures.
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Details
- Title
- Design Space Explorationfor Wireless Network-on-Chip Architectures
- Creators
- Paul William Wettin
- Contributors
- Partha P Pande (Advisor)Partha P Pande (Committee Member)Amlan Ganguly (Committee Member)Benjamin Belzer (Committee Member)Deukhyoun Heo (Committee Member)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Doctor of Philosophy (PhD), Washington State University
- Number of pages
- 106
- Identifiers
- 99900581737001842
- Language
- English
- Resource Type
- Dissertation