Design Techniques and Tradeoffs of FinFET SRAM Memories

Michael Allen Turi

Nine novel eight-transistor (8T) FinFET SRAM cell schemes using different shorted gate (SG) or low power (LP) FinFET configurations are studied and evaluated comprehensively in terms of leakage current, delay, read and write energy dissipation, energy delay product (EDP), and static noise margin. Comparisons to conventional 6T SRAM schemes reveal that the 8T SRAM schemes perform better, especially for a 32-bit by 1024-word (32x1024) array, since leakage current can be reduced by low-power schemes that reverse-bias the inverter transistors' back gates without adversely impacting read speed or read static noise margin. FinFETs provide significantly lower leakage current and higher on-current than bulk-CMOS transistors and allow the 8T FinFET SRAM schemes to greatly outperform 8T 32 nm CMOS SRAM cells. 8T SRAM configuration choices further affect these performance metrics. Reverse-biasing the inverter FinFETs' back gates can reduce leakage current by 2-97%. Additionally, FinFET SRAM cells designed for low-leakage are more effective than header and/or footer transistors added to a cell to reduce leakage current. For a 32x1024 array, read delay is dominant and can be minimized by using SG configuration for the read transistors. These two performance metrics are chiefly responsible for determining the energy consumption of a SRAM array. Reverse-biasing the inverter FinFETs' back gates also minimizes leakage current and EDP variation due to parameter, voltage, and temperature (PVT) variations. The 8T LP_INV, low-power inverters, scheme uses these configurations and is the best-performing FinFET SRAM scheme at a 1 V VDD, and in particular the 8T LP_INV1.2 cell has 60% less EDP than the conventional 8T SG FinFET SRAM scheme and performs best under PVT variations. Similar relative performance is observed for the cells at 0.6 V near-threshold operation; most cells yield reduced EDP and the 8T LP_INV1.2 cell still performs best. However, these cells suffer increased changes in performance due to PVT variations and increased delay. The LP_INV1.2 cell is also the best-performing FinFET SRAM cell at near-threshold operation; however, the 8T LP_SGR cell has less performance variation for PVT variations. The tradeoff is that the LP_SGR cell has a slightly higher average EDP than the LP_INV1.2 cell.

Design Techniques and Tradeoffs of FinFET SRAM Memories

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