Design Techniques for Time-Based Signal Processors in Next-Generation Wireless Communication Transceivers

Chung-Ching Lin

doi:10.7273/000005044

The evolution of communication standards has led to exponential growth in data rates that requires new architectures for processing and transmitting data with low power consumption. These architectures have to support wider bandwidths while ensuring quality of service for both mobile- and fixed wireless and wired services which encumbers the underlying technology and require design innovations leveraging analog/mixed-signal/RF design techniques. This dissertation proposes two innovative circuit architectures suited to next-generation transceivers that address fundamental constraints in millimeter wave (mmW) communication and battery-constrained radios.The abundant spectral resources in mmW open opportunities in rapid localization, and Gb/s data transmission using beamforming technology. Apart from data communication, knowledge of the angle of arrival and departure are of utmost importance in practical beamformers, to perform localization and interference control in a dense deployed wireless network. This work investigates a true-time-delay (TTD) array enabling both fast beam-training at the receiving end with wideband data communications and thus create a reconfigurable multi-modal spatial signal processor. A large delay range is implemented across GHz-bandwidth to accelerate beam training using frequency-dependent probing beams. Preliminary prototype of a 4-element switched capacitor time-interleaved array was demonstrated. An unique frequency-to-angle mapping with 3.8 ns maximum delay and 800 MHz bandwidth in the beam-training mode is achieved. The proposed prototype achieves 614.4 MB/s with 16-QAM at 7.3% EVM during data communication. The second part of this dissertation addresses a fundamental limitation in spurious signatures of digital-intensive ultra-low-power (ULP) transmitter (TX). Frequency-multiplying TX benefits from the adoption injection-locked (IL) technique with high energy efficiency but trade-offs with large spurs violating the TX spectral specifications. The proposed solution used a self-aligned Type-I phase-locked loop (PLL) with the IL technique to to calibrate the frequency and phase error in the oscillator, thus, achieving significantly improved spur performance.Two designs with different types of loop filter were demonstrated to investigate tradeoffs among power consumption, loop bandwidth, and spur rejection. The two TXs achieve an energy efficiency of 66.97 pJ/bit and 12.5 pJ/bit respectively under on-off-keying modulation while delivering an output power of -14 dBm with over 60 dB spur suppression.

Design Techniques for Time-Based Signal Processors in Next-Generation Wireless Communication Transceivers

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