EXPLORING POWER-THERMAL-PERFORMANCE TRADE-OFFS IN 3D NETWORK ON CHIP-ENABLED MANY-CORE SYSTEMS

Dongjin Lee

High-performance and energy-efficient Network-on-Chip (NoC) architecture is one of the crucial components of the manycore processing platforms. A very promising NoC architecture recently proposed in the literature is the three-dimensional small-world NoC (3D SWNoC). Due to short vertical links in 3D integration and the robustness of small-world networks, the 3D SWNoC architecture outperforms its other 3D counterparts. However, the performance of 3D SWNoC is highly dependent on the placement of the links and associated routers. In this dissertation, we propose a sensitivity-based link placement algorithm (SEN) to optimize the performance of 3D SWNoC. The sensitivity of a link in a NoC measures the importance of the link. The SEN algorithm optimizes the performance of 3D SWNoC by calculating the sensitivities of all the links in the NoC and removing the least important link repeatedly. We compare the performance of SEN algorithm with simulated annealing and machine learning-based optimization algorithm. 3D NoC architectures suffer from high power density and the resultant thermal hotspots leading to functionality and reliability concerns over time. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency Island (VFI)-based power management and Reciprocal Design Symmetry (RDS)-based floor planning. We undertake a detailed design space exploration for 3D NoC by considering power-thermal-performance trade-offs. We consider a small-world network-enabled 3D NoC in this performance evaluation due to its superior performance and energy-efficiency compared to other existing 3D NoC. For TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. Due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric and monolithic inter-tier vias offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. We present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts.

EXPLORING POWER-THERMAL-PERFORMANCE TRADE-OFFS IN 3D NETWORK ON CHIP-ENABLED MANY-CORE SYSTEMS

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