Dissertation
FUTURE OF WIRELESS SENSOR SYSTEM-ON-CHIPS: VOLTAGE-BASED VS. TIME-BASED SENSING TECHNIQUES
Washington State University
Doctor of Philosophy (PhD), Washington State University
01/2021
DOI:
https://doi.org/10.7273/000002461
Handle:
https://hdl.handle.net/2376/121059
Abstract
Future wearable and implantable medical devices require energy harvesters to relax the stringent system power budget and realize unlimited device lifetime. CMOS wireless sensor SoCs that directly operate under various energy harvesters are in urgent demand to avoid the efficiency loss during traditional voltage boosting. Contrary to a voltage-based system, time-based circuit decouples the need for high gain amplifier and promises to be highly compatible with ultra-low voltage operation. In this thesis, we focus on exploring ultra-low voltage design techniques for both voltage- and time-domain readout. In the voltage-domain readout, an energy-efficient low noise instrumentation amplifier (LNIA) is introduced with a unique class-AB biased inverter-based amplifier stage and a built-in ripple reduction loop. An ultra- low power successive approximation register analog-to-digital converter (SAR-ADC) and a temperature-compensated relaxation oscillator are also implemented on-chip. In the time-domain readout, a current-controlled relaxation oscillator replaces the ring oscillator to realize a single-bit noise shaping direct sensor-to-digital front-end with enhanced linearity. The time-domain calibration loop (TDCL) presented in this thesis mitigates the high signal-to-noise and distortion ratio (SNDR) sensitivity related to the KVCO variation. Lastly, an ultra-low power mostly-digital 915 MHz frequency multiplication transmitter (TX) with injection locking (IL) technique is introduced. The reference spur due to IL is remedied by a real-time phase correction loop combined with a notch filter. All three implementations are verified with fabricated silicon while achieving state-of-the-art performance. Measured with a biofuel cell-based natural energy harvester, the LNIA consumes 3.09 uW power while achieving a noise efficiency factor and power efficiency factor of 1.63 and 1.46, respectively. The time-domain readout consumes a total power of 0.22 uW with an SNDR of 63.2 dB. The SNDR variation is measured to be only 1.7 dB with more than 50% supply variation with the help of the TDCL. Operating under on-off-keying, the TX consumes an average power of 200.9 uW with a data rate of 3 Mb/s achieving an energy efficiency of 66.97 pJ/bit.
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Details
- Title
- FUTURE OF WIRELESS SENSOR SYSTEM-ON-CHIPS: VOLTAGE-BASED VS. TIME-BASED SENSING TECHNIQUES
- Creators
- Huan Hu
- Contributors
- Subhanshu Gupta (Advisor)Deuk Hyoun Heo (Committee Member)Dae Hyun Kim (Committee Member)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Doctor of Philosophy (PhD), Washington State University
- Publisher
- Washington State University
- Number of pages
- 277
- Identifiers
- 99900606856601842
- Language
- English
- Resource Type
- Dissertation