Dissertation
HIGH PERFORMANCE WIRELESS VERTICAL LINKS WITH SCALABLE TIME-DOMAIN MIXED-SIGNAL PROCESSING FOR 3D NETWORK-ON-CHIP
Doctor of Philosophy (PhD), Washington State University
01/2018
Handle:
https://hdl.handle.net/2376/111668
Abstract
Wireless interconnects using near-field inductive coupling (NFIC) enables contactless vertical communications necessary for the design of energy efficient and robust 3-D manycore systems. However, the achievable performance, energy efficiency, bandwidth, and associated area overhead of NFICs are intertwined imposing significant design challenges and tradeoffs to explore the optimum link configuration. To address these challenges, in this work, a holistic design approach is proposed for exploring energy-efficient NFICs and target to exploit the benefits of the NFICs in the context of efficient and reliable network-on-chip (NoC) design. The proposed design framework employs statistical link analysis to select optimum NFIC-link configuration and is significantly more efficient in terms of energy efficiency and area overhead compared to the state-of-the-art counterparts. We demonstrate that 3-D NoCs incorporating NFIC-enabled links outperform through-silicon-via (TSV) counterparts. In addition, the overall reliability of TSV- and NFIC-enabled hybrid 3-D NoC is significantly better than only TSV-based NoCs in order to counteract the electromigration and workload-induced stress challenges.In addition, this work also presents an echo-canceller-less wireless-wireline hybrid 3D interconnect for simultaneous bidirectional (SBD) vertical communication. This is accomplished by combining wireless near-field inductive coupling channel (NFIC) that encompasses wireline through-silicon via (TSV) channels to form a bidirectional vertical link for the first time using face-to-back 3D integration technologies applicable for multi-layer vertical communication. In experimental demonstration, the transceiver simultaneously communicates at an effective data rate of 6 Gb/s consuming 290 fJ/bit over the NFIC and TSV channels in 65nm CMOS process. The developed hybrid interconnect architecture exhibits more than 2x improved link performance over state-of-the-art 3D SBD link.
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Details
- Title
- HIGH PERFORMANCE WIRELESS VERTICAL LINKS WITH SCALABLE TIME-DOMAIN MIXED-SIGNAL PROCESSING FOR 3D NETWORK-ON-CHIP
- Creators
- Srinivasan Gopal
- Contributors
- Deukhyoun Heo (Advisor)Partha Pande (Committee Member)Daehyun Kim (Committee Member)
- Awarding Institution
- Washington State University
- Academic Unit
- School of Electrical Engineering and Computer Science
- Theses and Dissertations
- Doctor of Philosophy (PhD), Washington State University
- Number of pages
- 93
- Identifiers
- 99900581818301842
- Language
- English
- Resource Type
- Dissertation