LOCAL OSCILLATOR SIGNAL GENERATION FOR LARGE SCALE ARRAYS

DIPAN KAR

doi:10.7273/000007890

Millimeter-wave phased arrays are useful for efficient power combining, beam steering for imaging and detection, and high-speed wireless data links over 1–10 meters. However, their maximum antenna gain is limited by their effective aperture or physical size. Large array gain is highly desirable for enabling increased communication distances and higher resolution imaging/radar systems, which need narrow beams (typically diffraction limited by aperture). While prior work in phase arrays offers excellent performance for their intended applications, each was implemented with all array elements on a single chip. These existing arrays first generate a mm wave local oscillator (LO) using a single Phase-Locked Loop (PLL) locked onto an external reference crystal oscillator, and then distribute this LO to each pixel on chip. A single-chip implementation using a single PLL limits scalability to larger array sizes and effective apertures due to several factors: the maximum die size is constrained by its impact on chip yield, LO distribution network losses become excessively high for large arrays, and physical limitations are imposed by the wafer size. In addition to this, the power consumption is also significantly higher. Given these constraints, phase array systems formed across multiple dies or even wafer sections are needed for implementing larger arrays. While constructing an array across multiple dies is conceptually simple, LO distribution becomes more challenging. A multichip array’s LO path is susceptible to interconnect and assembly losses of PCB traces, bumps, and bond wires, whereas small on-chip arrays rely on low-loss mm-wave LO distribution. This proposed work is mainly divided into two parts. First project involves a 14 GHz < 90fs ultra-low jitter Sub-sampling PLL (SSPLL) design occupying an area of < 1mm2. The second project involves a fast-startup crystal oscillator design to start the crystal within 30 us of time. Our proposed fast start-up oscillator uses a novel Delta-sigma Modulator (DSM)-based injection technique and a 1 MHz real-time clock generation. The SSPLL and Crystal oscillator are fabricated using 65 nm CMOS technology. The SSPLL will generate the high-frequency LO signal for mixers to upconvert and downconvert the IF and RF signals for the RF transceivers. The crystal oscillators will generate the reference signal for the SSPLL.

LOCAL OSCILLATOR SIGNAL GENERATION FOR LARGE SCALE ARRAYS

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