NP-Separate: a new VLSI design methodology for area, power, and performance optimization

MONZURUL ISLAM DEWAN

doi:10.7273/000005058

Standard cells facilitate rapid time-to-market even for complex microprocessors when used in very-large-scale integration (VLSI). Consequently, standard cells are used in most digital VLSI layouts. NP-Separate, a novel design methodology proposed in this study that significantly improves the performance, power consumption, and layout area (PPA) of a VLSI design over the traditional standard-cell-based design. NP-Separate employs NP cells assembled by merging and routing N cells (only NFETs) to P cells (only PFETs), respectively. This provides more freedom of flexibility than conventional standard cells by taking advantage of fine-controlling transistor sizes independently. Simulation results show that NP-Separate notably reduces the PPAs, power-delay products, and energy-delay products compared to standard-cell-based designs. However, the NP cell formation steps should be automated to design large circuits. Therefore, design automation algorithms are developed to create NP cells automatically that dramatically shorten the design time, the coupling capacitance, the critical path delay, and the power consumption compared to manual NP-Separate designs. Additionally, a detailed placement algorithm allowing cell overlapping is presented to create more compact VLSI layouts when the automated process is applied. This combined effect reduces the metrics even more than the manual NP-Separate approach. Incorporating NP-Separate and monolithic three-dimensional (M3D) integration brings an exciting era of layout design. An M3D integration architecture enables ultra-thin silicon tier stacking. Contrary to conventional planar fabrication technologies, high-density stacking has smaller footprints, shorter wirelengths, higher performance, and lower power consumption, enhancing its appeal. Several steps are involved in the physical design of M3D integrated circuits, including 3D placement, clock-tree synthesis, routing, and pre/post-optimization. Due to numerous routing blockages, 3D routing is among the most time-consuming. Therefore, researchers proposed 3D routers that insert monolithic inter-layer vias (MIVs) and perform tier-by-tier routing in two sub-steps. In this work, an algorithm is shown to build a routing topology database of all multilayer monolithic rectilinear Steiner minimum trees (AMM-RSMTs) on the 3D Hanan grid that is used to construct timing-driven 3D routing topologies and perform congestion-aware global routing on 3D designs to validate the efficacy of the database. The algorithm and the database are anticipated to enable 3D routers to slash MIV insertion time and improve 3D routing quality.

NP-Separate: a new VLSI design methodology for area, power, and performance optimization

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