THE DEVELOPMENT OF DEPENDENCY-RESOLVING ARITHMETIC UNITS FOR HIGH-PERFORMANCE COMPUTING

Jihee Seo

doi:10.7273/000004400

The demand of compute-intensive applications is increasing and high-performance computing becomes more important. Various scientific computations such as partial differential equations, trigonometric functions, and matrix computations are performed in the compute-intensive applications. Solving an equation used in scientific computing is very complex and time-consuming. This scientific equation is a sequence of basic arithmetic operations such as addition, multiplication, and division. Since these basic operations take less time when hardware accelerators are used instead of software routines, these complex operations need to be performed by hardware accelerators. Thus, it is necessary to develop high-performance hardware accelerators and hardware algorithms for arithmetic operations. Although high-performance computing allows faster computation of a single instruction, it does not guarantee shorter execution time when multiple instructions are given. This is because of data dependencies among instructions and it is one of the most challenging issues. Hardware techniques such as a register renaming, dynamic pipeline scheduling and the system-level forwarding paths can alleviate the impact of the data dependencies, however, these cannot resolve data dependencies fundamentally and this leads to the serious performance degradation especially in compute-intensive application such as scientific computing. This performance degradation is from the fact that the dependent instruction cannot be processed with incomplete operands. In order to resolve a root cause of this performance degradation, the accelerator can process partially given input operands and also generate the partial output bits. In this dissertation, we focus on the development of arithmetic units to resolve the data dependencies for throughput improvement. Before designing the dependency-resolving units, the impact of dependency-resolving units on throughput of the processor is studied. After that, two types of new multiplier architectures are designed to resolve data dependencies and improve the throughput. These architectures use pipelining and intra-unit forwarding paths. Two types of pipeline schemes are used and each scheme resolves the different level of data dependency. The datapath of the multiplier is evenly pipelined and each stage can process partial input operands forwarded by intra-unit forwarding path from the later stage. After the analysis of the basic dependency-resolving multiplier architectures, these architectures are applied to the existing high-performance multipliers and these applications are compared. Furthermore, a new type of division algorithm is proposed to resolve the dependencies in division and it is called the interval-analysis based division. Since it does not use intermediate remainders and redundant binary, it can process partially given operands and also does not have any convergence issue. In addition, based on proposed division algorithm, the hardware algorithms for both high-throughput and high-speed dividers are proposed. For better performance and efficient use of resources, the speedup technique and the incremental update are used. In this dissertation, two high-speed dividers and four high-throughput dividers are presented and all these designs are based on interval analysis proposed in this work. These six dividers are compared with three different types of existing dividers.

THE DEVELOPMENT OF DEPENDENCY-RESOLVING ARITHMETIC UNITS FOR HIGH-PERFORMANCE COMPUTING

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