Dissertation
ULTRA-LOW POWER, COMPACT CLOCK GENERATION TECHNIQUES FOR NEXT-GENERATION COMMUNICATION SYSTEMS
Washington State University
Doctor of Philosophy (PhD), Washington State University
12/2024
DOI:
https://doi.org/10.7273/000007199
Abstract
The rapid advancement in data center processing speeds, driven by Artificial Intelligence (AI) and Machine Learning (ML) applications, necessitates high-frequency operation of wireline clock and data recovery (CDR) systems. This evolution demands low-power, high-resolution phase interpolators (PIs) in clocking circuits to precisely eliminate phase and frequency offsets between receivers and transmitters. Additionally, as data rates escalate in wireless communications, transmitted signals become increasingly vulnerable to interference, necessitating beamforming or beam steering techniques. An increase in the number of channels enhances the signal-to-noise ratio (SNR) at the receiver output
but also requires more PIs, potentially escalating power consumption and compromising the efficiency of the beamforming system. Therefore, the development of low-power PIs is critical for enabling efficient beamforming at higher frequencies.
This dissertation presents two novel PI architectures designed to address these critical challenges. The first architecture is a constant slope and swing ramp-based PI designed for baseband beamforming delay compensation. This PI, implemented in TSMC-65nm CMOS, is both linear and low-power, with a power efficiency of 0.312 mW/GHz. It can operate at frequencies up to 1.6 GHz and compensate for signal delays with bandwidths up to 800 MHz. However, its low swing slope signal ramp-signal induces more noise, resulting in jitter of 412 fs. The second architecture is a DC-modulated ramp-based PI, which significantly increases the operating speed to 12 GHz- seven times that of the first PI architecture. This low-power PI implemented in 65nm CMOS shows a power efficiency of 0.18 mW/GHz. This PI can directly generate 4-phase PI outputs at clock frequencies up to 6 GHz without requiring a delay-locked loop (DLL) or quad generator at the input side, making it a most compatible low power clocking solution for CDR applications. Additionally, it contributes to minimum noise at the output with jitter of 68fs only.
The third contribution of this dissertation is the design of a low-power, compact analog sub-sampling phase-locked loop (SS-PLL) using a capacitor-multiplier circuit to reduce the area of the loop filter and the overall PLL footprint. This approach offers superior phase noise performance compared to digital PLLs, presenting a promising solution for high-performance RF transceivers in 5G communication systems.
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Details
- Title
- ULTRA-LOW POWER, COMPACT CLOCK GENERATION TECHNIQUES FOR NEXT-GENERATION COMMUNICATION SYSTEMS
- Creators
- Soumen Mohapatra
- Contributors
- Deukhyoun Dr. Heo (Chair)Subhanshu Dr. Gupta (Committee Member)Partha Pratim Pande (Committee Member)
- Awarding Institution
- Washington State University
- Academic Unit
- School of Electrical Engineering and Computer Science
- Theses and Dissertations
- Doctor of Philosophy (PhD), Washington State University
- Publisher
- Washington State University
- Number of pages
- 109
- Identifiers
- 99901195339501842
- Language
- English
- Resource Type
- Dissertation