Thesis
40 Gbps SiGe pattern generator IC with variable clock skew and output levels
Washington State University
Master of Science (MS), Washington State University
2006
Handle:
https://hdl.handle.net/2376/103321
Abstract
A single-chip 40 Gbps pattern generator design in 0.18 µm SiGe BiCMOS technology is described. An on-chip 128x128 bit RAM with an access time of 3 ns stores the data pattern. A hybrid 128:1 CMOS/ECL multiplexer increases the output data rate from the RAM to 40 Gbps. The output driver is back terminated with 50 ohms and provides programmable levels in the range -2 V to 2 V into a 50 ohm load. The simulated pattern dependent jitter is under 1 ps at all output levels. The clock can be delayed by a programmable number of clock cycles plus a vernier delay of up to 50 ps in 0.2 ps steps in simulation. Power dissipation is up to 1.5 W depending on the output amplitude and termination voltage.
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Details
- Title
- 40 Gbps SiGe pattern generator IC with variable clock skew and output levels
- Creators
- Matthew John Zahller
- Contributors
- George S. La Rue (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; Pullman, Wash. :
- Identifiers
- 99900525297901842
- Language
- English
- Resource Type
- Thesis