Thesis
A 16 Bit 500KSps low power successive approximation analog to digital converter
Washington State University
Master of Science (MS), Washington State University
2009
Handle:
https://hdl.handle.net/2376/102365
Abstract
A 16 Bit, 500KSps low power successive approximation analog-to-digital converter (ADC) is designed in JAZZ 0.18um SiGe CMOS process using only CMOS devices. The speed of 500KSps is achieved by interleaving between two capacitor arrays with shared input buffer. Power efficient comparators with shutdown mode are designed to reduce the power consumption of the ADC. Capacitance ratio error, offset error and gain error of the ADC are calibrated using self-calibration circuits. Rail-to-rail input buffer is designed to drive the ADC. The ADC works under ± 1V power supplies, ± 0.8V references and a 10MHz clock. The total power dissipation is 4.59mW including the input buffer and the noise is 25.1uV with the input buffer and 16.9uV without. The SNDR, ENOB of the ADC are 87.4dB, 14.22 bits. The FOM of the ADC with and without the input buffer is 240.5fJ/Conv. Step and 44.0fJ/Conv. Step respectively.
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Details
- Title
- A 16 Bit 500KSps low power successive approximation analog to digital converter
- Creators
- Kun Yang
- Contributors
- Geroge S. La Rue (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; Pullman, Wash. :
- Identifiers
- 99900524802201842
- Language
- English
- Resource Type
- Thesis