Thesis
A 5 GHz digitally controlled synthesizer in 90nm CMOS
Washington State University
Master of Science (MS), Washington State University
2009
Handle:
https://hdl.handle.net/2376/103440
Abstract
This thesis presents the implementation of a self-calibrating low-power Digitally Controlled Synthesizer (DCS) operating at 5 GHz in the IBM 90nm process. The DCS has high tolerance to device and process variations because of its mostly digital design. It provides an extremely wide tuning range with fine resolution. The DCS also has low power consumption and a small layout area. A novel time-to-delay accumulator is used that prevents the need to propagate the carries of a digital adder using two separate delay lines. A 5GHz three bit Johnson counter is described and its use as a frequency divider. A second 10-bit, 5 GHz synchronous counter using complementary logic is also described. The 24-bit time-to-delay accumulator provides 300 Hz frequency resolution and incorporates single-event upset (SEU) mitigation circuitry. The use of Reverse Body Biasing is also discussed to reduce the effects of Total Ionizing Dose (TID) radiation. The implementation of capacitive loaded 0-300ps delay lines is covered in detail as well as a novel calibration scheme for the delay lines. The DCS has a built-in calibrator to correct for process and environmental variations in the delay. The DCS is also designed so that the added delay can be calibrated to within 2ps of resolution without interfering with normal operation of the DCS. The paper includes a brief description of the conditions for oscillation, Phase Locked Loops (PLL), ring oscillator VCO, LC VCO, and Discrete Digital Frequency Synthesizer (DDFS). The simulation results for the operation of the DCS, which was simulated using Synopsis HSPICE, and Mentor ADMS. Future test procedures of the actual chip using scan chain flip flops are covered as well. The paper concludes with a discussion of future work and project contributions.
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Details
- Title
- A 5 GHz digitally controlled synthesizer in 90nm CMOS
- Creators
- Bill Hamon
- Contributors
- George S. La Rue (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; Pullman, Wash. :
- Identifiers
- 99900525146201842
- Language
- English
- Resource Type
- Thesis