Thesis
A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits
Washington State University
Master of Science (MS), Washington State University
2017
Handle:
https://hdl.handle.net/2376/102290
Abstract
Three-dimensional (3-D) integration is becoming a promising technology providing numerous benefits such as lower power consumption, higher latency, wider bandwidth, and smaller form factor than two-dimensional (2-D) integration. To fully benefit from 3-D integration, industrial standards, computer-aided design (CAD) tools, and new design methodologies and algorithms will need to be developed targeting for the special feature of 3-D integration. The design of monolithic three-dimensional integrated circuits (3-D ICs) requires 3-D placement, 3-D clock tree synthesis, 3-D routing, and 3-D timing and power optimization. In this thesis, we propose a placement legalization algorithm for the design of multi-tier gate-level monolithic 3-D ICs to generate high-quality layouts. The algorithm utilizes uniform location scaling and planar and z-direction partitioning to perform native 3-D legalization. We compare the proposed algorithm with an existing legalization algorithm and show that the proposed algorithm achieves shorter wirelength with almost no density constraint violation.
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Details
- Title
- A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits
- Creators
- Yiting Chen
- Contributors
- Dae Hyun Kim (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; [Pullman, Washington] :
- Identifiers
- 99900524876301842
- Language
- English
- Resource Type
- Thesis