Thesis
A self-calibrating low power 16-bit 500KSps charge-redistribution SAR analog-to-digital converter
Master of Science (MS), Washington State University
2008
Handle:
https://hdl.handle.net/2376/102957
Abstract
This thesis presents an implementation of a self-calibrating low-power 16-bit 500 KSps charge redistribution successive approximation register based analog-to-digital converter (CR ADC) to be used with a sensor integrated circuit (IC) built for neurosensory application. The CR ADC uses a time-interleaving-by-2 architecture, shutting down amplifiers when not in use, and switching between comparators to reduce power consumption. Furthermore, the CR ADC corrects the capacitor-ratio error of the binaryweighted capacitor arrays, common-mode errors due to parasitics, offset error due to mismatches and charge injection from the control switches, and gain error due to parasitics to improve linearity and accuracy. The CR ADC has an input range of ± 1V, SNDR of 89.01dB with an effective resolution of 14.49 bits, SFDR of 89.5dB, FOM factor of 116.3 fJ / conversion step, and dissipates an average power of 4.23mW including the input buffer, while operating at ± 1.5V power supply. The proposed ADC was designed in TSMC 0.25µm CMOS process. Further performance enhancement can be achieved to push the accuracy above 15 bits while lowering down power and noise.
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Details
- Title
- A self-calibrating low power 16-bit 500KSps charge-redistribution SAR analog-to-digital converter
- Creators
- Prasanna Upadhyaya
- Contributors
- George S. La Rue (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Identifiers
- 99900525126501842
- Language
- English
- Resource Type
- Thesis