Thesis
ANALYSIS AND DESIGN OF AN ULTRA-LOW POWER LOW-NOISE DTMOS BASED INSTRUMENTATION AMPLIFIER APPLIED TO THE PHYSIOLOGICAL SIGNAL ACQUISITION SYSTEM
Washington State University
Master of Science (MS), Washington State University
01/2021
DOI:
https://doi.org/10.7273/000003107
Handle:
https://hdl.handle.net/2376/123092
Abstract
With the rapid development of Internet of Things (IoT) technology and the popularity of portable devices, portable medical devices will become widely available soon. Physiological signal monitoring sensors are widely used for personal health management and long-term healthcare monitoring, especially for preventing acute illnesses and chronic disease monitoring for pediatric and elderly. Physiological signal monitoring sensors have the ability to monitor people's behavior in real-time for various daily activities, such as physiological signals that exhibit different waveforms and amplitudes when sleeping and awake. The real-time collected signals can be frequently compared to medical databases to detect abnormal health data for preventive healthcare. Therefore, an accurate and error-free system that provides high-quality monitoring of physiological signals is very important. Typically, an instrumentation amplifier (IA) is used for high accurate acquisition and amplification within this system. An IA with excellent performance gives patients safer health conditions and allows patients to have better health protection.
This work introduces an ultra-low-power instrumentation amplifier operating at sub-0.4V voltage. Using dynamic threshold voltage MOSFET (DTMOS). The DTMOS reduces threshold voltage further and increases the driven current while the device is operating. Therefore, the DTMOS-based folded-cascode has been chosen, resulting in an increases the common-mode rejection ratio (CMRR) of the circuit while increasing the output signal swing compared over conventional topologies. The IA takes the benefit of the rail-to-rail common-mode feedback circuit and chopping to reduce flicker noise and DC offset. Reducing the chip area and power consumption leads to the output signal's high signal-to-noise ratio (SNR). The post-simulation shows that the circuit archives 45dB gain, DC to 2.07KHz operating bandwidth, and 0.8μW total power consumption. The simulated CMRR is 103dB, with 80dB power supply rejection ratio (PSRR). The simulated input reference noise is 140nV/√Hz (@100Hz) with 7.27 Noise Efficiency Factor (NEF).
Keywords: Instrumentation Amplifier, DTMOS, rail-to-rail, chopping, clock boosting switch, physiological acquisition, bio-medical application.
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Details
- Title
- ANALYSIS AND DESIGN OF AN ULTRA-LOW POWER LOW-NOISE DTMOS BASED INSTRUMENTATION AMPLIFIER APPLIED TO THE PHYSIOLOGICAL SIGNAL ACQUISITION SYSTEM
- Creators
- Yuling Liu
- Contributors
- Subhanshu Gupta (Advisor)Dae Hyun Kim (Committee Member)Deuk Hyoun Heo (Committee Member)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University
- Number of pages
- 98
- Identifiers
- 99900651793101842
- Language
- English
- Resource Type
- Thesis