Thesis
An Ultra-Compact 14 GHz Integer-N Sub-Sampling PLL with RMS-Jitter of 85.4 fs for mm-Wave 5G Communications and Sensings
Washington State University
Master of Science (MS), Washington State University
2023
DOI:
https://doi.org/10.7273/000005315
Abstract
This thesis describes a 14-GHz sub-sampling PLL (SSPLL), as well as its phase noise analysis, optimization, and design for future 5G wireless transceivers. The theoretical and measured performance improvements of the phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption are presented. The proposed capacitor multiplier shrinks the loop filter capacitor size by 28 times. The active capacitor is boosted to reduce out-of-band phase noise while consuming less power. The SSPLL is built in a 65-nm CMOS process with a core active area of 0.0918 mm2 and operates at 1.2-V supply, achieving a tuning range of 13.1-14.8 GHz, 85.4-fs integrated jitter at 14 GHz, 8.12-mW power consumption, and -252.4 dB figure-of merit (FoM). The measured in-band and out-of-band phase noises were -108.6 dBc/Hz at 1-MHz offset and -128.9 dBc/Hz at a 10-MHz offset, respectively.
Metrics
11 File views/ downloads
179 Record Views
Details
- Title
- An Ultra-Compact 14 GHz Integer-N Sub-Sampling PLL with RMS-Jitter of 85.4 fs for mm-Wave 5G Communications and Sensings
- Creators
- DIPAN KAR
- Contributors
- Deuk Hyoun Heo (Advisor)Subhanshu Gupta (Committee Member)Noel N Schulz (Committee Member)Ganapati Bhat (Committee Member)
- Awarding Institution
- Washington State University
- Academic Unit
- School of Electrical Engineering and Computer Science
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University
- Number of pages
- 60
- Identifiers
- 99901031039401842
- Language
- English
- Resource Type
- Thesis