CNTFET logic gate design with tolerance to metallic CNTs

Florian Grigoleit

Due to CMOS technology limitations to scale down, it is necessary to consider an alternative technology to allow further improvements in computers and digital circuits. One possible approach is Carbon-Nanotube Field Effect Transistors (CNTFETs). Since the first CNTFET was introduced, one of the major challenges in this research area has been the fabrication of semiconductor carbon nanotubes. So far it has not been possible to produce only semiconducting nanotubes. Instead, there has always been a certain percentage of non-semiconducting CNTs, called metallic carbon nanotubes. Without the ability to switch between conducting and not-conducting they can be considered as faulty transistors. Until today, it has not been possible to reduce the number of metallic nanotubes to an extremely low, thus an acceptable, level. While it is essential to further reduce the number of metallic tubes, it is also necessary to design integrated circuits (ICs) tolerant to these metallic CNTs to form transistors. Such ICs are required to keep functioning with a reasonable v percentage of metallic tubes while maintaining the advantages of CNTFETs towards CMOS, including reduced energy dissipation and increased speed. In this thesis a design approach is proposed and evaluated to achieve a high level tolerance towards metallic CNTs while keeping the circuit small and efficient. This design consists of an approach using single nanotubes for multiple transistors simultaneously with several tubes in series, thus ensuring the functionality of the logic gate while keeping the number of CNTs and the additional consumption of energy and area moderate. The simulations for this thesis have been conducted with Synopsys HSPICE using the Stanford University Carbon Nanotube Field Effect Transistor (CNFET) HSPICE Model by J. Deng et. H.S. P. Wong [1][2][3]. It was shown that with a presumed percentage of 90% / 95% semiconducting CNTs the advisable number of tubes in series is two or three while presuming a lower percentage of functioning tubes requires a higher number of tubes. When evaluating the design on larger circuits one goal was to determine the largest feasible number of gates per tube as well as measuring the occurring leakage power. It was found, that in circuits with gates with more than four inputs a design consisting of multiple smaller gates suffers from less delay than large single-gates.

CNTFET logic gate design with tolerance to metallic CNTs

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