Thesis
H-tree based configuration schemes for a reconfigurable DSP architecture
Master of Science (MS), Washington State University
2005
Handle:
https://hdl.handle.net/2376/350
Abstract
Reconfigurable computing has attracted considerable attention recently because of the potential to deliver the performance of application-specific hardware along with the flexibility of general-purpose computers. Many reconfigurable architectures have been proposed in the last few years, however, few discussions have been conducted on the specifics of the reconfiguration scheme itself. This thesis describes two efficient configuration schemes for a reconfigurable DSP hardware that utilizes an H-tree interconnection network to link clusters of logic blocks, or cells, to map the desired circuits. The schemes make use of the existing hardware in a two-level reconfigurable cell array for communication of configuration data. The result is a speedy configuration that requires minimal additional control wires and hardware. Circuit simulations indicate that a configuration speed of 1 GHz can be achieved using a modest 0.18-[mu]m CMOS technology.
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Details
- Title
- H-tree based configuration schemes for a reconfigurable DSP architecture
- Creators
- Andy Widjaja
- Contributors
- José G. Delgado-Frias (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Identifiers
- 99900525169001842
- Language
- English
- Resource Type
- Thesis