Thesis
High-speed backplane with broadcast capability
Washington State University
Master of Science (MS), Washington State University
2003
Handle:
https://hdl.handle.net/2376/147
Abstract
A high-speed point to multi-point, loop-through backplane was designed and implemented. The prototype consists of a motherboard with segmented differential bus lines and loop-through active connectors bridging the gap between any given two segments. The 50 Ω characteristic impedance differential bus lines have minimal stubs at connections to the active connectors and operation above 2 Gbps is expected. Approximately 6 pairs of bus lines per inch was achieved in the prototype. The daughter boards are placed 1" apart with a transceiver buffer on each and connectors to communicate with external hosts. The transceiver is a tri-state buffer that is designed and fabricated using IBM 5HP SiGe technology and operates to about 10 Gbps.
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Details
- Title
- High-speed backplane with broadcast capability
- Creators
- Qian Wang
- Contributors
- George S. La Rue (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; Pullman, Wash. :
- Identifiers
- 99900525010301842
- Language
- English
- Resource Type
- Thesis