Optimizing the performance of direct digital frequency synthesizers for low-power wireless communication systems

David James Betowski

A direct digital frequency synthesizer (DDFS) generates a highly accurate sine wave using feed-forward digital signal processing, overcoming many of the problems incurred with the traditional analog closed-loop frequency synthesizer, the Phase-Locked Loop (PLL). The most popular application of a DDFS is generating the variable carrier frequency required in portable wireless communication systems, which require both high accuracy and very low power consumption. A three-level abstraction analysis and design approach is presented. The system level analysis focuses on selecting an appropriate phase-to-sine wave approximation circuit, which has traditionally been implemented with a large-sized ROM lookup table, resulting in a moderately high SFDR and very high power consumption. Recent solutions reduce the ROM size by using a segmented linear approximation to compute the sine wave in real-time. The solutions produce a very high SFDR (using up to 64 segments), but the circuit complexity remains high. A novel segmented parabolic approximation is introduced, and using only 16 segments, yields an 84 dBc SFDR. The circuit complexity is lower than other methods having a similar SFDR Both the new approximation and the DDFS, in general, require several high-speed arithmetic components, including 8 - 32-bit adders and a Wallace-tree based multiplyaccumulate circuit. Pipelining the DDFS system may be necessary if high-speed operation is desired. A mathematical model is presented at the component level to determine the optimal number of stages with respect to the speed and power requirements. Descending to the circuit level, four logic gate styles (complementary, pseudo-NMOS, dynamic, and differential cascode voltage switch) are constructed and simulated in three different CMOS processes to analyze the speed and power consequences of process scaling. Presented is a fresh investigation of significantly reducing the power-delay product by lowering the supply voltage to sub-threshold levels. It is shown that a 100-fold energy decrease does not require the added non-recurring engineering costs of scaling down to a smaller CMOS process.

Optimizing the performance of direct digital frequency synthesizers for low-power wireless communication systems

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