Thesis
Performance evaluation of wireless Networks on Chip
Washington State University
Master of Science (MS), Washington State University
2009
Handle:
https://hdl.handle.net/2376/103776
Abstract
The Network-on-Chip (NoC) paradigm has emerged as an enabling methodology to integrate numerous numbers of embedded cores in a single die[1, 2]. The performance gain arising out of adopting NoC is constrained by the performance limitation of the wireline interconnects. With technology scaling, the global wires are quickly becoming the performance obstacle in terms of data communication latency and energy dissipation. Hence, designing the interconnection infrastructure for multi-core chips becomes a major challenge. To alleviate the problems of high latency and energy dissipation in a NoC, different alternative options have been envisioned including wireless NoC, 3D NoC, photonic NoC, and RF-I NoC. In this thesis, we evaluate the performance improvement of the wireless NoCs (WiNoCs) in terms of throughput and latency, and it is compared with the performance of 3D NoCs and traditional 2D wireline NoCs.
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Details
- Title
- Performance evaluation of wireless Networks on Chip
- Creators
- Jyun-Lyang Chang
- Contributors
- Partha Pratim Pande (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; Pullman, Wash. :
- Identifiers
- 99900525162401842
- Language
- English
- Resource Type
- Thesis