Thesis
Physical design of monolithic 3D integrated systems and memory
Washington State University
Master of Science (MS), Washington State University
12/2020
DOI:
https://doi.org/10.7273/000004175
Handle:
https://hdl.handle.net/2376/118599
Abstract
Introduction of monolithic inter-tier via (MIV) has opened new possibilities in three-dimensional (3D) VLSI design techniques. In this thesis, we propose a non-slicing 3-D floorplan representation to design block-level monolithic 3-D ICs. The new 3-D floorplan representation applied to simulated annealing-based optimization achieves smaller volume, shorter wire length, and lower dynamic power consumption than the Sequence Triple, Sequence Quintuple, and Slicing Tree 3-D floorplanning representations. The smaller size and reduced parasitics of MIV compared to through-silicon via (TSV) make designing cache memory in 3D a good choice. 3D cache memory is expected to achieve better performance with the number of layers increases. In this thesis, we explore different 3D memory design techniques and compare their power, delay, footprint, and energy-delay-product (EDP) values. First, we propose a new design methodology named Compact that consumes less power, incurs smaller delay and overall, shows better EDP compared to traditional 3D memory design techniques. Then we propose a new three-dimensional computer architecture to reduce context switch overhead.
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Details
- Title
- Physical design of monolithic 3D integrated systems and memory
- Creators
- Shatonu Das
- Contributors
- Dae Hyun Kim (Advisor) - Washington State University, Electrical Engineering and Computer Science, School of
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University
- Identifiers
- 99900890768801842
- Language
- English
- Resource Type
- Thesis