Schemes for reducing power and delay in SRAMs

Katie Ann Blomster

Static random-access memories (SRAMs) are used in a wide variety of applications ranging from ICs to embedded systems. As the demand for systems to reduce power consumption and increase speed continues to grow, these design requirements are passed on to a system's components, including SRAMs. In this thesis a number of novel schemes for reducing power and delay in SRAMs are presented. Memory access incorporates two different operations: the memory read and the memory write. To improve the performance of the memory write operation, seven different memory cell designs are proposed. Each of these designs has been extensively simulated in 180-nm CMOS technology for comparison with the standard six-transistor (6T) differential memory cell. The three cells performing the best in terms of energy consumption, delay and the energy-delay product demonstrate improvements of 27.6%, 12.3%, and 24.1% over the 6T cell, which uses 27.75 fJ and has an overwrite delay of 83.24 ps each write cycle. The memory read circuitry is modified at the column level as well as the cell level. To save the power used in pre-charging and pulling down the bit-lines each read access, the precharge signal and its pull-up transistors are removed. A series of bit-line pull-up schemes that only switch the bit-lines when necessary are discussed and the most effective designs are simulated thoroughly using 180-nm CMOS technology. In comparison with the standard reading design, the novel delayed bit-line capture pull-up (DBCP) scheme yield minimum energy savings of 44.3% and improves delay by at least 22.7%. To ensure that the read logic works in conjunction with the memory write, four different test SRAMs containing the novel read designs are built in 90-nm technology. Each novel SRAM is compared with the standard SRAM implementation, which has a delay of 474.3 ps and dissipates an average of 521.3 fJ over a row of memory cells. The best results are achieved by the DBCP min style SRAM, with 28.6% power savings and a 39.6% improvement in delay. A discussion of the design tradeoffs when using a novel reading scheme is also included.

Schemes for reducing power and delay in SRAMs

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