Thesis
Schemes to reduce power in FPGA implementations of the advanced encryption standard
Washington State University
Master of Science (MS), Washington State University
2007
Handle:
https://hdl.handle.net/2376/102607
Abstract
Since its introduction in 2001 the Advanced Encryption Standard has been the subject of vast amounts of research in such areas as speed of encryption, size of encryption device, ultra low power encryption, and algorithm integrity. One area that has been relatively neglected is the area of power conscious encryption. This focus is intended to reduce the average power consumption of an encryption core while maintaining a similar level of performance so that it can be easily and reliably integrated into systems with varying requirements. In this thesis three designs will be proposed to achieve this goal of power efficient encryption. This includes a standard data in/data out design, a key storage design, and a multistage design. These designs along with two reference designs, from NIST and the Open Cores project, will be analyzed to determine their power consumption rates utilizing Xilinx XPower and Mentor Graphics' ModelSim software packages. Once the preliminary analysis has been completed, the architecture of the designs will be examined along with the effects of FPGA choice and clock rate to obtain a better understanding of how to satisfy the stated goal and to further optimize the proposed designs to meet that goal. When analyzing the proposed designs, it was shown that the most promising design used 201 mW or 20.7% less power then the best performing reference design when using a Virtex II FPGA. Similarly when using a Spartan 3 FPGA the results showed the proposed design used 37.9 mW or 18% less power than the best performing reference design. Additionally by reducing the clock rate of an FPGA the design's power can be reduced to less than six percent of the chip's total required power, with 94% of the power being allocated to satisfy the quiescent power requirements. The proposed designs' individual component power analysis also showed that no component consumed more power than was expected, based on the individual component's complexity.
Metrics
Details
- Title
- Schemes to reduce power in FPGA implementations of the advanced encryption standard
- Creators
- Jason Daniel Van Dyken
- Contributors
- José G. Delgado-Frias (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; Pullman, Wash. :
- Identifiers
- 99900525139001842
- Language
- English
- Resource Type
- Thesis