Thesis
Single-ended 16x8 Gbps data bus in 90nm CMOS
Washington State University
Master of Science (MS), Washington State University
2009
Handle:
https://hdl.handle.net/2376/102521
Abstract
This thesis presents the design of a high-speed single-ended 16 channel data bus for chipto-chip communication with each channel capable of providing up to 8Gbps of throughput and adding up for a total bus throughput of 128 Gbps. By using singe-ended signaling instead of the commonly used differential signaling, each channel requires only one I/O pin and one physical channel for transmitting data compared to two I/O pins and two channels required for differential signaling. Although some overhead is added, the single-ended bus still requires only 21 physical channels for transmission instead of the 32 that would be required for a differential bus. A printed circuit board was fabricated to model the physical channels and to decide the best possible arrangement for the channels. Some design features commonly used for high-speed data communication like pre-emphasis and equalization are employed. The equalization schemes are tunable for each channel and therefore allows for different channel lengths. Also, some issues associated with single-ended signaling, like higher crosstalk, absence of common-mode rejection and power supply bounce, were investigated and methods to resolve them were implemented to ensure reliable communication.
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Details
- Title
- Single-ended 16x8 Gbps data bus in 90nm CMOS
- Creators
- Saurabh Mandhanya
- Contributors
- George S. La Rue (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Publisher
- Washington State University; Pullman, Wash. :
- Identifiers
- 99900525059101842
- Language
- English
- Resource Type
- Thesis