Thesis
VLSI implementation of cross-parity and modified dice fault tolerant schemes
Master of Science (MS), Washington State University
2004
Handle:
https://hdl.handle.net/2376/203
Abstract
Fault-tolerant approaches to digital system design are becoming increasingly important, in particular for mission critical systems. In this document, two implementations of a fault-tolerant cell for a reconfigurable DSP processor are described. This cell is centered around a 32-bit memory which is used as a lookup table inside the processor. Fault-tolerance is implemented through the use of a cross-parity scheme and a modifided DICE (Dual-Interlocked storage Cell) design. The cross-parity scheme is a system-level approach that computes and stores parity bits during write operations, and uses these bits during memory reads to identify errors in the system. One error can be corrected during every read operation of the cell. A prototype for this system has been fabricated in 0.5µm CMOS VLSI technology. The modified DICE design is a circuitlevel approach that utilizes redundancy and feedback to quickly correct transient errors inside of individual memory latches. The benefits and drawbacks of both approaches will be compared and analyzed.
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Details
- Title
- VLSI implementation of cross-parity and modified dice fault tolerant schemes
- Creators
- Daniel Ryan Blum
- Contributors
- José G. Delgado-Frias (Degree Supervisor)
- Awarding Institution
- Washington State University
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Theses and Dissertations
- Master of Science (MS), Washington State University
- Identifiers
- 99900524859601842
- Language
- English
- Resource Type
- Thesis