A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance

Journal article

Peer reviewed

Mitchell J Myjak and JosÉ G Delgado-Frias

IEEE transactions on very large scale integration (VLSI) systems, Vol.16(1), pp.14-23

01/2008

Handle:

https://hdl.handle.net/2376/116843

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Title: A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Creators: Mitchell J Myjak
JosÉ G Delgado-Frias
Publication Details: IEEE transactions on very large scale integration (VLSI) systems, Vol.16(1), pp.14-23
Academic Unit: Electrical Engineering and Computer Science, School of
Identifiers: 99900548252001842
Language: English
Resource Type: Journal article