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A mesochronous pipelining scheme for high-performance digital systems
Journal article

A mesochronous pipelining scheme for high-performance digital systems

S.B Tatapudi and J.G Delgado-Frias
IEEE transactions on circuits and systems. I, Regular papers, Vol.53(5), pp.1078-1088
05/2006
Handle:
https://hdl.handle.net/2376/111525

Abstract

High performance Uncertainty mesochronous pipeline Digital systems multiplier Performance gain Registers Synchronization register delays Pipeline processing CMOS technology Logic pipelined system Clocks Propagation delay

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