Journal article
A pipelined architecture for ray/bezier patch intersection computation
Canadian journal of electrical and computer engineering, Vol.28(1), pp.27-35
01/2003
Handle:
https://hdl.handle.net/2376/113336
Abstract
An algorithm for computing ray/B ezier patch intersections is described from a hardware design perspective. This algorithm uses patch subdivision and other geometrical techniques to find a given maximum number of intersection points nearest to the ray origin. A pipeline-based hardware architecture is proposed, the number of pipeline stages required is verified by simulation, and the performance of a load-balanced implementation based on a state-of-the-art digital signal processor is estimated.
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Details
- Title
- A pipelined architecture for ray/bezier patch intersection computation
- Creators
- R.R LewisRenwei Renwei WangD Hung
- Publication Details
- Canadian journal of electrical and computer engineering, Vol.28(1), pp.27-35
- Academic Unit
- Engineering and Applied Sciences (TRIC), School of
- Publisher
- IEEE Canada
- Identifiers
- 99900547773501842
- Language
- English
- Resource Type
- Journal article