Journal article
A two-level reconfigurable architecture for digital signal processing
Microelectronic engineering, Vol.84(2), pp.244-252
2007
Handle:
https://hdl.handle.net/2376/117776
Abstract
This paper describes a novel reconfigurable architecture for digital signal processing (DSP). This architecture consists of a two-level array of cells and interconnections. On the upper level, fundamental DSP operations such as multiplication and addition are mapped onto blocks of 4-bit cells. On the lower level, each cell uses a 4
×
4 matrix of smaller “elements” to perform the necessary computations. Cells also contain pipeline latches for increased throughput. The architecture features a simple VLSI implementation that combines the flexibility of memory elements with the speed of DOMINO logic. Initial prototypes have been fabricated using a modest 0.5-μm CMOS technology. Circuit simulations of the cell in 0.25-μm technology indicate that the design achieves a clock frequency of 200
MHz.
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Details
- Title
- A two-level reconfigurable architecture for digital signal processing
- Creators
- M.J MyjakJ.G Delgado-Frias
- Publication Details
- Microelectronic engineering, Vol.84(2), pp.244-252
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Publisher
- Elsevier B.V
- Identifiers
- 99900547984301842
- Language
- English
- Resource Type
- Journal article