Design, synthesis, and test of networks on chips

P.P Pande; C Grecu; A Ivanov; R Saleh; G De Micheli

doi:10.1109/MDT.2005.108

Back

Design, synthesis, and test of networks on chips

Journal article

Open access

Design, synthesis, and test of networks on chips

P.P Pande, C Grecu, A Ivanov, R Saleh and G De Micheli

IEEE design & test of computers, Vol.22(5), pp.404-413

09/2005

DOI: https://doi.org/10.1109/MDT.2005.108

Handle:

https://hdl.handle.net/2376/114276

Files and links (1)

url

https://doi.org/10.1109/MDT.2005.108View

Published (Version of record) Open

Abstract

VLSI

VLSI Systems

Switches

Throughput

Wire

Delay

Wiring

Automatic synthesis

Network-on-a-chip

Bandwidth

and Fault-Tolerance

Network synthesis

Reliability

Testing

Clocks

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.

Metrics

8 Record Views

See more details

Details

Title: Design, synthesis, and test of networks on chips
Creators: P.P Pande - Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
C Grecu
A Ivanov
R Saleh
G De Micheli
Publication Details: IEEE design & test of computers, Vol.22(5), pp.404-413
Academic Unit: Electrical Engineering and Computer Science, School of
Publisher: IEEE Computer Society
Identifiers: 99900547818601842
Language: English
Resource Type: Journal article