Journal article
High-Performance Low-Power Selective Precharge Schemes for Address Decoders
IEEE transactions on circuits and systems. II, Express briefs, Vol.55(9), pp.917-921
09/2008
Handle:
https://hdl.handle.net/2376/115886
Abstract
Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND-NOR and sense amplifier (sense-amp) decoders, are compared to the NOR decoder using 90-nm CMOS technology. The sense-amp decoder dissipates between 29.5% and 50.1% and the AND-NOR decoder dissipates between 73.7% and 104.4% of the energy dissipated by the NOR decoder. The delay of the Sense-Amp decoder is 69.2% and the delay of the AND-NOR decoder is 80.8% of the nor decoder delay.
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Details
- Title
- High-Performance Low-Power Selective Precharge Schemes for Address Decoders
- Creators
- M.A Turi - Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WAJ.G Delgado-Frias - Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA
- Publication Details
- IEEE transactions on circuits and systems. II, Express briefs, Vol.55(9), pp.917-921
- Academic Unit
- Electrical Engineering and Computer Science, School of
- Publisher
- IEEE
- Identifiers
- 99900548491201842
- Language
- English
- Resource Type
- Journal article