Journal article
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
IEEE transactions on computers, Vol.54(8), pp.1025-1040
08/2005
Handle:
https://hdl.handle.net/2376/114600
Abstract
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.
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Details
- Title
- Performance evaluation and design trade-offs for network-on-chip interconnect architectures
- Creators
- Partha Pratim Partha Pratim Pande - Dept. of Electr. & Comput. Eng., British Columbia Univ., BC, CanadaC Grecu - Dept. of Electr. & Comput. Eng., British Columbia Univ., BC, CanadaM Jones - Dept. of Electr. & Comput. Eng., British Columbia Univ., BC, CanadaA Ivanov - Dept. of Electr. & Comput. Eng., British Columbia Univ., BC, CanadaR Saleh - Dept. of Electr. & Comput. Eng., British Columbia Univ., BC, Canada
- Publication Details
- IEEE transactions on computers, Vol.54(8), pp.1025-1040
- Publisher
- IEEE
- Identifiers
- 99900548140101842
- Language
- English
- Resource Type
- Journal article