Testing Network-on-Chip Communication Fabrics

C Grecu; A Ivanov; R Saleh; P.P Pande

doi:10.1109/TCAD.2007.907263

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Testing Network-on-Chip Communication Fabrics

Journal article

Open access

Peer reviewed

Testing Network-on-Chip Communication Fabrics

C Grecu, A Ivanov, R Saleh and P.P Pande

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.26(12), pp.2201-2214

12/2007

DOI: https://doi.org/10.1109/TCAD.2007.907263

Handle:

https://hdl.handle.net/2376/117066

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Abstract

Costs

Multicore processing

Design methodology

Built-in self-test

Interconnect infrastructure

network-on-chip (NoC)

Automatic testing

Network-on-a-chip

test optimization

unicast test

Computer architecture

Parallel processing

multicast test

Fabrics

System-on-a-chip

Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed methodology offers a tradeoff between test time and on-chip self-test resources. The fault models used are specific to deep submicrometer technologies and account for crosstalk effects due to interwire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to the components under test in a recursive manner. It exploits the inherent parallelism of the data transport mechanism to reduce the test time and, implicitly, the test cost. We also describe a suitable test-scheduling approach. In this manner, the test methodology developed in this paper is able to reduce the test time significantly as compared to previously proposed solutions, offering speedup factors ranging from 2x to 34x for the NoCs considered for experimental evaluation.

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Details

Title: Testing Network-on-Chip Communication Fabrics
Creators: C Grecu - Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
A Ivanov - Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
R Saleh - Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
P.P Pande
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.26(12), pp.2201-2214
Academic Unit: Electrical Engineering and Computer Science, School of
Publisher: IEEE
Identifiers: 99900548395101842
Language: English
Resource Type: Journal article